TOP > NCKU GICRC-Semiconductor Division
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Prof. Takayuki OHBA(Specially Appointed)(Concurrent Post) | |||
| Room | S9 | Mail-Box | S9-11 | |
| TEL | 03-5734-2211 | |||
| takayuki.ohba(at)first.iir.isct.ac.jp Please replace “(at)” with “@”. | ||||
| HomePage | https://www.wow.first.iir.isct.ac.jp/ | |||
| Research Field | BBCube LSI Semiconductor Process Development and Applications | |||
| Objective | To develop the cutting-edge BBCube three-dimensional large-scale integration technology and drive the semiconductor industry beyond scaling. | |||
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| Bumpless vertical interconnects between wafers | |
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Prof. Kuan-Neng CHEN(Specially Appointed)〔Ito Lab〕(Concurrent Post) | |||
| Room | J3 | Mail-Box | J3-132 | |
| TEL | 045-924-5866 | |||
| chien.k.0dea(at)m.isct.ac.jp Please replace “(at)” with “@”. | ||||
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Prof. Norio CHUJO(Specially Appointed)〔Ito Lab〕(Concurrent Post) | |||
| Room | R2棟 | Mail-Box | R2-32 | |
| TEL | 045-924-5083 | |||
| chuujou.n.813f(at)m.isct.ac.jp Please replace “(at)” with “@”. | ||||
| HomePage | https://www.wow.first.iir.isct.ac.jp/ | |||
| Research Field | Design and architecture of BBCube 3D integration | |||
| Objective | Development of semiconductor technologies that achieve both high performance and low. | |||
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| BBCube 3D configuration ・Multi-xPU/IVR/Multi-Memory Vertical Stack ・WOW and COW Hybrid Processes ・Cu-Damascene Via-Last TSVs) |
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Prof. Takashi YODA(Specially Appointed)〔Ohba Lab〕(Concurrent Post) | |||
| Room | R2棟 | Mail-Box | R2-32 | |
| TEL | 045-924-5083 | |||
| takashi.yoda(at)first.iir.isct.ac.jp Please replace “(at)” with “@”. | ||||
| HomePage | https://www.wow.first.iir.isct.ac.jp/ | |||
| Research Field | Wide Band Gap (WBG) Semiconductor Technology | |||
| Objective | Development of the High performance SiC/(GaN) devices | |||
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| Lifetime measurement for n-Buffer SiC layer | Hyperspectral Raman Imaging of 4H-SiC BPD |
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Prof. Young Suk KIM(Visiting)〔Ito Lab〕(Concurrent Post) | |||
| Room | J3 | Mail-Box | J3-132 | |
| TEL | 045-924-5866 | |||
| youngsuk.k.aa(at)m.titech.ac.jp Please replace “(at)” with “@”. | ||||
| HomePage | http://www.wow.pi.titech.ac.jp/ | |||
| Research Field | Process Integration Development for 3D LSI Devices | |||
| Objective | To develop ultra-thinning of 300-mm device wafers and those stack process integration technology for three-dimensional LSI technology. Because the physical interconnects length becomes 1/10 using ultra-thin wafers and Wafer-on-Wafer (WOW) process, high performance 3D devices with low power consumption will be realized. | |||
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Thinned DRAM 300mm wafer